| Top Articles for IEEE Transactions on Circuits and Systems I PDFs Downloaded from January - December 2008 |
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| Source of Statistics: IEEE Xplore weblogs. Note: These are not COUNTER-compliant usage statistics, which means they have not been scrubbed for automatic download tools. See worksheet for ranking of periodical titles based on overall 2008 usage. | |||
| Article Title | Volume | Issue | 2008 Jan - Dec Use By Article |
| Full On-Chip CMOS Low-Dropout Voltage Regulator | 54 | 9 | 1628 |
| A frequency compensation scheme for LDO voltage regulators | 51 | 6 | 1354 |
| A 1-V CMOS Current Reference With Temperature and Process Compensation | 54 | 7 | 1173 |
| A DC-DC charge pump design based on voltage doublers | 48 | 3 | 1111 |
| Phase noise in oscillators: a unifying theory and numerical methods for characterization | 47 | 5 | 953 |
| The design of low-noise bandgap references | 43 | 4 | 885 |
| VCO Design With On-Chip Calibration System | 53 | 10 | 802 |
| Low-noise amplifier design for ultrawideband radio | 51 | 6 | 795 |
| An Ultra-Low-Power Long Range Battery/Passive RFID Tag for UHF and Microwave Bands With a Current Consumption of 700 nA at 1.5 V | 54 | 7 | 768 |
| Analysis of multistage amplifier-frequency compensation | 48 | 9 | 723 |
| Analysis of charge-pump phase-locked loops | 51 | 9 | 714 |
| Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation | 52 | 12 | 710 |
| Behavioral modeling of switched-capacitor sigma-delta modulators | 50 | 3 | 674 |
| Power supply rejection ratio in operational transconductance amplifiers | 37 | 9 | 658 |
| A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers | 53 | 8 | 647 |
| Analysis of the PLL jitter due to power/ground and substrate noise | 51 | 12 | 635 |
| Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC/DC PWM Converters | 55 | 2 | 622 |
| Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC | 55 | 5 | 617 |
| Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme | 52 | 8 | 594 |
| A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors | 54 | 11 | 581 |
| Low-Power CMOS Rectifier Design for RFID Applications | 54 | 6 | 575 |
| Development of Integrated Broad-Band CMOS Low-Noise Amplifiers | 54 | 10 | 545 |